1. Field of the Invention
The present invention generally relates to depositing a barrier layer on a semiconductor substrate.
2. Description of the Related Art
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions (e.g., less than about 0.20 micrometers or less), whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increase. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 4:1, and particularly where the aspect ratio exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free and seam-free sub-micron features having high aspect ratios.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology because copper has a lower resistivity than aluminum, (about 1.7 μΩ-cm compared to about 3.1 μΩ-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Copper metallization can be achieved by a variety of techniques. A typical method generally includes physical vapor depositing a barrier layer over a feature, physical vapor depositing a copper seed layer over the barrier layer, and then electroplating a copper conductive material layer over the copper seed layer to fill the feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
However, one problem with the use of copper is that copper diffuses into silicon, silicon dioxide, and other dielectric materials which may compromise the integrity of devices. Therefore, conformal barrier layers become increasingly important to prevent copper diffusion. Tantalum nitride has been used as a barrier material to prevent the diffusion of copper into underlying layers. However, the chemicals used in the barrier layer deposition, such as pentakis(dimethylamido) tantalum (PDMAT; Ta[NH2(CH3)2]5), may include impurities that cause defects in the fabrication of semiconductor devises and reduce process yields. Therefore, there exists a need for a method of depositing a barrier layer from a high-purity precursor.